Hybrid tester architecture

ABSTRACT

A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input circuitry and clock input circuitry and shared timing circuitry coupled to the clock input circuitry. The shared timing circuitry generates programmed timing signals. Per-pin data circuitry couples to the data input circuitry and generates drive data and expected data values associated with each individual device pin. The per-pin formatting circuitry responds to the programmed timing signals to produce tester waveforms in accordance with the per-pin data.

FIELD OF THE INVENTION

[0001] The invention relates generally to automatic test equipment, andmore particularly to a hybrid semiconductor tester architecture fortesting semiconductor devices.

BACKGROUND OF THE INVENTION

[0002] Automatic test equipment provides the ability for semiconductordevice manufacturers to test each and every device made. By testing eachdevice, the manufacturer can sort devices having like speeds, and/orseparate failed devices from passing devices. In this manner, themanufacturer is able to confidently put fully functioning devices intothe marketplace.

[0003] Testing a semiconductor device typically involves applyingsignals to specified pins according to precise timings, and detectingthe device outputs in response to the applied signals. The detectedoutput signals are then compared to expected values to determine whetherthe device operated within a specified range of parameters. Many of thehigh-level design considerations for a semiconductor tester focus on themanner of applying and detecting signals to and from thedevice-under-test (DUT).

[0004] With this in mind, semiconductor tester architectures usuallyfall within one of two types, shared resource, or tester-per-pin. In aconventional tester-per-pin architecture, such as that shown in FIG. 1,each tester channel 10 includes separate tester resources for assignmentto one pin of a DUT. Those resources include the necessary timingcircuitry 12, pattern generation circuitry 14, formatting circuitry 16,and pin electronics 18 for applying signals to, or receiving signalsfrom a pin of the DUT 20. A failure processing circuit handles theevaluation of expected test data versus actual data. This architectureis highly desirable when testing complex logic devices that needflexibility in testing the individual device pins.

[0005] Shared resource architectures, on the other hand, are most oftenfound in memory testers, where multiple devices are testedsimultaneously to maximize throughput and minimize test costs. Aconventional shared resource architecture is shown in FIG. 2,illustrating shared resources for a 2048 channel tester. In thisexample, sixty-four memory devices 40 (each having thirty-two pins) maybe tested with, for example, thirty-two copies 40 of the timing 42,formatting 44, and pattern generation (or data generation) circuitry 46.Fanout circuitry 48 distributes the shared formatted tester signals inparallel to the multiple DUTs 30.

[0006] After testing the devices on a shared resource tester, thefailure data is typically stored in a bit-image failure memory known asa catchram 50, and subsequently downloaded to redundancy analysiscircuitry 52. After the data is analyzed by the redundancy analyzers, arepair solution is sent to a laser repair station 60, along with thefailed devices, where the redundant lines identified for use inrepairing the device are programmed into operation.

[0007] While the conventional shared resource architecture works wellfor many test applications, and are often far less costly than theirper-pin counterparts, different DUTs typically have bits that fail indifferent rows and/or columns. Consequently, the repair schemes fordifferent devices will be different.

[0008] Moreover, some device manufacturers choose to repair devices onthe tester without delays inherent in transmitting failure data toseparate repair stations. Repairing DUTs on the tester generallyinvolves writing unique repair data after testing to each device toactivate internal device fuses corresponding to the desired repairsolution. However, without having the ability to write the individualdata for each device pin to each device, the device manufacturer cannotrepair the devices in this manner. As a result, many manufacturers optfor the more expensive per-pin tester architectures in order toaccomplish on-tester device repair.

[0009] What is needed and currently unavailable is a low-cost hybridtester architecture solution that provides the per-pin benefits ofunique device failure identification with the shared-resource advantagesof low-cost. The hybrid tester architecture of the present inventionsatisfies these needs.

SUMMARY OF THE INVENTION

[0010] The hybrid tester architecture of the present invention providesa way to preserve the low cost attributes of shared resource testerswithout sacrificing data generation flexibility. To realize theforegoing advantages, the invention in one form comprises a hybridtester architecture for testing a plurality of semiconductor devices inparallel. The hybrid tester architecture includes per-pin formattingcircuitry having data input circuitry and clock input circuitry andshared timing circuitry coupled to the clock input circuitry. The sharedtiming circuitry generates programmed timing signals. Per-pin datacircuitry couples to the data input circuitry and generates drive dataand expected data values associated with each individual device pin. Theper-pin formatting circuitry responds to the programmed timing signalsto produce tester waveforms in accordance with the per-pin data.

[0011] Other features and advantages of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The invention will be better understood by reference to thefollowing more detailed description and accompanying drawings in which

[0013]FIG. 1 is a high-level block diagram of a conventional per-pintester architecture;

[0014]FIG. 2 is a high-level block diagram of a conventional sharedresource tester architecture; and

[0015]FIG. 3 is a high-level block diagram of a hybrid testerarchitecture according to one form of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0016] The hybrid tester architecture of the present invention providesa low-cost way to test semiconductor devices in parallel whilepreserving device data uniqueness. This is done by employing sharedresources for certain tester functions, and per-pin resources for otherfunctions. As a result, on-tester device repair is achievable with alow-cost tester.

[0017] Referring now to FIG. 3, the hybrid tester architecture accordingto one form of the present invention, generally designated 100, includesa computer workstation 102 and a tester body 104 (in phantom). Thetester body includes channel resources that define a hybrid testerarchitecture sufficient to test a plurality of DUTs 106 in parallel. Afailure memory 115 and redundancy analysis circuitry 117 cooperate withthe channel resources to test and repair the devices as more fullydescribed below.

[0018] Further referring to FIG. 3, the hybrid channel resources includeshared-pin timing circuitry 108, per-pin formatting circuitry 110, andper-pin data generation circuitry 112. The shared-pin timing circuitrycomprises a set of thirty-two modules, or “copies” of the tester timingsystem resources for generating signals in parallel through the per-pinformatting circuitry 110 to the same “like” pin for all of the DUTs 106.

[0019] The per-pin formatting circuitry 110 preferably comprises digitalcircuitry in the form of a plurality of flip-flops (not shown), eachhaving a data input (not shown) and a clock input (not shown) forclocking in data in response to the timing signals. In this manner, thetiming signal may be synchronized to the data, as is well known in theart.

[0020] With continued reference to FIG. 3, the per-pin data generationcircuitry 112 preferably comprises a plurality of dedicated memoryblocks sufficient to store unique data for each pin of the DUTs 106. Inthe example where sixty-four devices are tested in parallel, each devicehaving thirty-two pins, 2048 memory blocks are available to provide theper-pin data resources. Preferably, the memory blocks are realized asRAM memories to minimize costs.

[0021] Consistent with the example above, each of the per-pin memoryblocks feeds its output to a corresponding per-pin formatting circuit110 (for a total of 2048 blocks). As noted above, the per-pin data getsclocked through the per-pin formatting circuitry by the shared-pintiming circuitry 108.

[0022] Prior to operation, the per-pin data generation resources 112 areprogrammed to provide identical data values for each of the thirty-twosets of shared timing resources 108. In this sense, the data generationcircuitry may be viewed as “shared” at this stage of testing. This isbecause each of the DUTs 106 are identical, and go through the sameinitial test patterns in order to determine faults.

[0023] As testing progresses, each of the DUTs 106 undergoes write andread operations so that the tester can determine if any of the DUTs havefaulty cells, and if so, where those cells lie. The failure data foreach DUT 106 is routed through respective databuses 111 (shown inphantom) and stored in the failure memory 115, as is well known in theart.

[0024] Following completion of the test, the failure data from thefailure memory 115 is fed to the on-tester redundancy analysis circuitry117. The circuitry analyzes the faulty data for each DUT and assignsredundant rows and columns (built into each DUT) to “fix” the device.Each redundancy solution is unique for a particular DUT (the redundantrow/column addresses) and generally involves programming the DUT toincorporate certain row and column address lines. For on-tester devicerepair, the solution data is fed back to the computer workstation 102.Once the solutions are known, corresponding test patterns are createdand fed to the per-pin data resources 112 to then generate writeaddresses for programming activation of the desired redundancy elementsfor each device.

[0025] If desired, a second test may be performed on the devices toverify the acceptability of the repair solutions for each device.

[0026] Those skilled in the art will appreciate the many benefits andadvantages afforded by the present invention. Of significant importanceis the preservation of low cost for testing semiconductor devices inparallel through use of shared timing and formatting resources, yetmaximizing tester flexibility through the implementation of per-pin dataresources.

[0027] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetail may be made therein without departing from the spirit and scopeof the invention. For example, while the description herein has focusedon memory testers and memory devices, the invention may be utilized onlogic devices where per-pin timing is unnecessary. This provides a verylow-cost solution to testing logic devices.

What is claimed is:
 1. A hybrid tester architecture for testing andrepairing a plurality of semiconductor devices in parallel, eachsemiconductor device having a predetermined number of pins, the hybridtester architecture including: a computer workstation; per-pinformatting circuitry having data input circuitry and clock inputcircuitry; shared timing circuitry coupled to the clock input circuitry,the shared timing circuitry operative to generate programmed timingsignals; and per-pin data circuitry coupled to the data input circuitry,the per-pin data circuitry operative to generate drive data associatedwith each individual device pin; whereby the per-pin formattingcircuitry is responsive to the programmed timing signals to generatetester waveforms in accordance with the per-pin data.
 2. A hybrid testerarchitecture according to claim 1 wherein: the per-pin data circuitrycomprises a plurality of memory blocks, each memory block correspondingto one of the predetermined number of pins.
 3. A hybrid testerarchitecture according to claim 1 and further including: a capturememory for storing fail data relating to the plurality of semiconductordevices; and redundancy analyzer circuitry for processing the failuredata into a repair solution.
 4. A hybrid tester architecture accordingto claim 3 wherein the redundancy analyzer is coupled to the computerworkstation and operative, after generating repair solutions, totransmit the repair solutions to the computer workstation.
 5. A methodof testing a plurality of semiconductor devices, each of the deviceshaving a plurality of pins and redundant row and column addresses, themethod including the steps: generating test data unique to each of theplurality of pins; clocking the unique test data through uniqueformatting circuitry with shared timing signals; applying the testsignals to the plurality of semiconductor devices; detecting and storingfailure data relating to the plurality of semiconductor devices;analyzing the failure data to generate repair solutions for activatingcertain of the redundant rows and columns for each of the plurality ofsemiconductor devices; routing the repair solutions back to the computerworkstation; and programming the plurality of semiconductor devices toactivate the desired redundant rows and columns based on the repairsolutions.